It is widely believed that mankind is entering the third era of cognitive computers. Cognitive computers may extend the boundaries of human cognition by deriving insights and intelligence from the vast amount of data at our disposal. Today's cognitive computers are still based on the von Neumann computing architecture that is highly area/power inefficient due to the physical separation between memory and logic. To address this challenge, an alternative brain inspired neuromorphic computing architecture is heavily researched—either to complement the existing cognitive computers or to replace them in the long run. However, to fully realize the areal/power benefits of such architecture, it is essential to realize the synaptic and possibly the neuronal elements using nanoscale memristive devices. Memristive devices are resistive devices whose resistance depends on the history of the current that had previously flown through it. They can be arranged in high-density crossbar arrays and each memristor can be used to store multiple bits of information. These properties make memristors a suitable to be used as synapses in neuronal networks, in which is a vast amount of synapses with analog values. However, memristors have limitations such as nonlinearity, limited dynamic range, a symmetric conductance response and devise variability that pose a key challenge. To achieve satisfactory network performance, it is essential to have a linear symmetric device with enough dynamic range.
There are several disclosures relating to a method providing a multi-memristive synaptic element for a cognitive computing system. For example, US 20150170028 A1 discloses a method of providing memristive devices in a neural network and updating weights of each synapse between an input layer neuron and an output layer neuron, wherein the weight is spike timing modulated with updates. This method may be used for pattern recognition. Additionally, the method includes classifying a spike pattern represented by a set of inter-spike intervals, regardless of noise in the spike pattern.
Further, US 20090292661 A1 discloses a method of utilizing memristor arrays in neural networks and implementing synaptic weight updates. The document pertains to compact synaptic circuits and networks comprising compact synaptic circuits that exhibit functional characteristics of biological synapses and networks of synapses including, but not limited to, spike timing dependent plasticity.
However, it is a known disadvantage of traditional approaches to address and synchronize sub-elements of the memristor devices even if arrays of memristors are used.
Hence, there may be a need to overcome the limitations of traditional approaches, namely the nonlinearity of memristors and a coordination of individual elements of a memristor array used as synaptic elements.